The present invention relates to ion implantation apparatus and method, and more particularly to ion implantation apparatus and method for obtaining non-uniform ion implantation energy.
Generally, in order to manufacture a semiconductor device, particularly, a semiconductor memory device, such as a Dynamic Random Access Memory (DRAM), various unit processes are required. The unit processes include a stacking process, an etching process, and an ion implantation process, and are usually performed on a wafer. In the ion implantation process, dopant ions, such as boron and arsenic, are accelerated and pass through the surface of a wafer. Electric characteristics of a material can be changed by the above ion implantation process.
The ion implantation into the wafer is achieved by moving the wafer in the direction of the Y-axis, and scanning an ion beam in the direction of the X-axis and implanting the ion beam into the wafer. In the above ion implantation, ions are implanted into all regions of the wafer at the same dose and energy. This is preferable to the ion implantation process, but is not preferable to other unit processes. That is, as a result of various unit processes, thicknesses and etching degrees of obtained films over all regions of the wafer are not uniform. The reason is that many variables of the unit processes cannot be accurately controlled. Accordingly, process errors due to the process variables, which are not expected or accurately controlled, occur.
For example, critical dimensions (hereinafter, referred to as CDs) representing the widths of the gate electrodes are different according to regions of a wafer. That is, the CD of the gate electrode at the center of the wafer may be relatively large, and the CD of the gate electrode at the edge of the wafer may be relatively small. On the other hand, the CD of the gate electrode at the center of the wafer may be relatively small, and the CD of the gate electrode at the edge of the wafer may be relatively large. The above difference of the CDs is caused by the uncontrolled variables of the unit processes. In case that the CD of the gate electrode at the center of the wafer is larger than the CD of the gate electrode at the edge of the wafer, the threshold voltage of a device at the center of the wafer is larger than the threshold voltage of a device at the edge of the wafer. In case that the CD of the gate electrode at the center of the wafer is smaller than the CD of the gate electrode at the edge of the wafer, the threshold voltage of the device at the center of the wafer is smaller than the threshold voltage of the device at the edge of the wafer.
Further, in order to form a source/drain having a Lightly Doped Drain (LDD) structure, spacers are formed on side surfaces of a gate stack, and source/drain ion implantation using the spacers as an ion implantation barrier is performed. Since the thickness of the spacers is not uniform over all regions of a wafer, the source/drain having the LDD structure has a non-uniform profile, thereby causing transistors to have non-uniform characteristics.